Altera5SGXMB9R2H43C2GFPGA
FPGA Stratix® V GXFamily 840000Cells 0.85V 1760-Pin FC-HFBGA Tray
| Compliant | |
| 3A001.a.7.b | |
| NRND | |
| 8542.31.00.60 | |
| SVHC | Yes |
| Automotive | No |
| PPAP | No |
| Stratix® V GX | |
| 28nm | |
| 600 | |
| 1268000 | |
| 0.85 | |
| Utilize Memory | |
| 840000 | |
| 704 (18x18) | |
| SRAM | |
| 53248 | |
| 2640 | |
| 2 | |
| RapidIO to AXI Bridge Controller (RAB)|Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Sub-frame Latency JPEG 2000 Encoder (BA130)|SPAUI MAC|RLDRAM II Controller Core | |
| Altera/Barco Silex/Mobiveil, Inc/Commsonic | |
| 840000 | |
| 32 | |
| 66 | |
| 14.1 | |
| 352 | |
| 4 | |
| Yes | |
| Yes | |
| No | |
| Yes | |
| 2 | |
| LVPECL|LVDS|HCSL | |
| LVTTL|LVCMOS | |
| DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|RLDRAM III|QDRII+SRAM | |
| 0.82 | |
| 0.88 | |
| 1.2|1.25|1.35|1.5|1.8|2.5|3 | |
| 0 | |
| 85 | |
| Commercial | |
| Stratix | |
| Befestigung | Surface Mount |
| Verpackungshöhe | 3.3 mm |
| Verpackungsbreite | 45 mm |
| Verpackungslänge | 45 mm |
| Leiterplatte geändert | 1760 |
| Standard-Verpackungsname | BGA |
| Lieferantenverpackung | FC-HFBGA |
| 1760 | |
| Leitungsform | Ball |
| EDA / CAD Models |
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