Terasic TechnologiesT0556Programmierbare-Logik-Entwicklungsplatinen und -kits

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The Intel Cyclone 10 GX FPGA Development Kit is an ideal starting point for applications, such as factory automation, video connectivity, or embedded vision or concept proving.

With this development kit, you can:

• Develop designs for Intel Cyclone 10 GX FPGAs

• Develop and test PCI Express* (PCIe*) 2.0 designs using the PCI-SIG*- compliant development board

• Direct connection via USB 3.1 Type C, small form-factor pluggable (SFP+), and RJ-45 connectors

• Develop modular and scalable designs by using direct connection or via the FPGA mezzanine card (FMC) connector to support protocols, such as USB 3.1 Gen2, GigE Vision, JESD204B, HDMI, Display Port, 12G serial digital interface (SDI), Serial Rapid I/O*, Common Public Radio Interface (CPRI), and IEEE 1588

Specification:

Intel Cyclone 10 GX FPGA.

• P/N: 10CX220YF780E5G with 220K logic elements (LEs)

Memory interfaces.

• 1 channel of x40 DDR3 SDRAM at 933 MHz

Communication ports

• 10/100/1000 Base-T Ethernet port with RGMII (LVDS)

• USB3.1 Type-C, supporting SuperSpeed, backward compatible with USB2.0

• 2 x SFP+ supporting 10GbE

• PCIe Gen2 x4

• FMC-LPC expansion

Clock sources

• 50 MHz oscillator, LVCMOS for FPGA core

• Programmable clock generator for FPGA core and transceiver (XCVR)

• 100 MHz for PCIe, from PCIe system to FPGA XCVR

• User-defined reference clock input from a FMC card

• External differential input through SMA, AC coupled

• Single-ended LVCMOS clock output through SMA, DC coupled

LED

• 1 x power LED

• 1 x config_done LED

• Parallel flash loader (PFL) load/error LED

• PFL program number LED

• Ethernet LEDs

• SFP+ LEDs

Push button

• 3 x user push buttons

• 1 x user program selection

• 1 x push button to initiate FPGA configuration

• 1 x push button to reset the FPGA logic

Switches

• User dual inline package (DIP) switches x4

• DIP switch for FPGA configuration scheme selection

• DIP switch for default image selection

• DIP switch for JTAG chain selection

• DIP switch for clock source selection

FPGA Configuration

• Active Serial (AS) x4 mode configuration with EPCQ-L

• Fast passive parallel (FPP) configuration mode

• Configuration via Protocol (CvP) with PCIe Gen2 x4

Power

• Intel Enpirion® point-of-load synchronous buck regulators with integrated inductors

• On-board power measurement and management

• Power-failure monitor

• 12V power input from PCIe system or external power adaptor input